1. Field of the Invention
The invention concerns a circuit arrangement with field-effect transistors for voltage level converting a TTL input signal into higher FET levels relative thereto. The invention is primarily suitable for integrated semiconductor storage components of data processing systems.
2. Description of the Prior Art
The integrated semiconductor storage systems used in present-day processors are mainly in FET technology. However, because of their higher switching speed, such data processors also use integrated circuits in bipolar technology at a number of points for example, for high-speed registers, logic means, etc. To ensure that a complex circuit network made up of bipolar and field-effect components functions satisfactorily, it is of course, necessary to observe the operating and control voltage levels required. As in typical cases the FET storage components referred to receive their input signals from the outputs of bipolar components, it is necessary to adapt the appertaining levels at such interfaces.
A voltage level scheme typical of circuits with bipolar transistors is the so-called TTL level scheme. For this purpose, it may be agreed, for example, that one binary state, e.g., logical "0", be represented by a voltage ranging from 0 to 0.6 V and the other binary state, e.g., logical "1", by a voltage value ranging from 2.4 to the operating voltage of, e.g., 5 V. In comparison with this, the control and operating voltages typical of FET circuits are noticeably higher. As a result, a field-effect transistor controlled in the worst case by an input signal of as little as 2.4 V for the upper binary state would be only relatively weakly conductive at a threshold voltage VT of about 1.5 V. In other words, a field-effect transistor thus controlled would still be relatively highly resistive even in its conductive state, so that a further circuit node, a load capacitance or the like could be discharged only comparatively slowly. For this reason, at the interfaces between bipolar and FET chips there were previously provided separate level converter chips in bipolar technology, the output voltages of which suited the specific input requirements of the FET components. However, in the course of further development the demand for fully TTL-compatible FET storage components has been increasing.
Input circuits comprising field-effect transistors and operated by means of input signals in the TTL level scheme are known, for example, from U.S. Pat. Nos. 3,739,194 and 4,063,119, as well as from the IEEE Journal of Solid-State Circuits, Vol. Sc-13, No. 3, June 1978, pp. 333 to 338, in particular FIG. 5 on page 335. The circuit situation described in these citations is such that the turn-on voltage (threshold voltage) of the input FET is lower than the voltage level of the input signal associated with the switch-off state. Thus, unless additional measures were taken, the input FET could not be reliably switched off by means of a TTL input signal. For the manufacture of the field-effect transistors it would rather be necessary to use a modified process ensuring that the field-effect transistors are designed for a higher threshold voltage (assuming, for example, that an N-channel enhancement FET is used). The input FET in accordance with the afore-mentioned citations is reliably switched off by raising its turn-on voltage above the switch-off level by means of a bias applied to the source electrode. However, such a rise disadvantageously affects the switch-on process of the input FET, so that, in accordance with the third citation, it can be reversed during the input signal phases.